In comparing circuits which compare the magnitude relation between an input analog signal and a reference signal, convert a comparison result into a signal of logical level, and output the signal, there is a problem that an error occurs in a base reference voltage due to a DC offset voltage caused by manufacturing variations in a transistor used therein or the like.
For example, in parallel analog-to-digital converters which include a resistor series that generates voltages at given intervals and a plurality of comparing circuits that use the generated voltages as reference voltages, and convert an input analog signal to a digital signal, it is known that desired resolution cannot be obtained unless the error caused by the DC offset voltage is reduced to a value substantially smaller than minimum resolution (LSB).
The error is reduced by use of a DC offset voltage correcting technique, so that the resolution can be improved.
A conventional DC offset voltage correcting technique is performed by providing a plurality of reference voltages at intervals substantially smaller than the LSB, and shifting the reference voltage in a direction to cancel the generated DC offset voltage.
The above conventional technique, however, has a problem that the number of resistors configuring the resistor series that generates the plurality of reference voltages at voltage intervals substantially smaller than the LSB is increased, so that the circuit area is larger.